The M21012 is a high-performance quad multi-rate clock and data recovery (CDR) array, optimized for multi-lane telecom, and datacom applications. Each channel has an independent multi-rate CDR capable of operating at data-rates between 42 Mbps and 3.2 Gbps, allowing maximum flexibility in system design. The M21011 is rated for operation in the range of 1 Gbps to 3.2 Gbps. The M21001 is rated for operation in the range of 42 Mbps to 800 Mbps. Aside from the difference in supported signal data-rates, the M21012, M21011, and M21001 are identical. Signal conditioning features include adaptive input equalization and output pre-emphasis, allowing robust reception and transmission of signals to other devices up to 60° away.
User-selectable input interface types allow DC-coupled input to CML, LVDS, and LVPECL. The outputs can also be DC-coupled to CML, LVDS and LVPECL. Frequency acquisition can be accomplished with or without an external reference clock. The built-in frequency synthesizer allows multi-rate operation, while operating with a single reference clock. The device can be controlled either through hardwired pins or an I2C-compatible interface. The hardwired mode eliminates the need for an external micro-controller, while allowing control of the key features of the device. The I2C-compatible interface allows complete control of the device features.
|M21012-11P||CMOS OC-3 to 3.2G QCDR||QFN / MLF||72|
|M21012-12||CMOS OC-3 to 3.2G QCDR IC||QFN / MLF||72|
|M21012-12P||CMOS OC-3 to 3.2G QCDR IC||QFN / MLF||72|
|M21012-31P||CMOS OC-3 to 3.2G QCDR for video apps IC||QFN / MLF||72|
|M21012EVM||CMOS OC-3 to 3.2G QCDR Eval Brd||EVM||N/A|
|M21012G-12||CMOS OC-3 to 3.2G QCDR (rohs pkg)||QFN / MLF||72|
|M21012GEVM||CMOS OC-3 to 3.2G QCDR Eval Brd RoHS||n/a||n/a|
|M21012VEVM||CMOS OC-3 to 3.2G QCDR Eval Brd - Video||EVM||N/A|
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