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M28525/9

Inverse Multiplexing for ATM (IMA) Family


Overview

Description

The M2852x family of devices provides system designers with a complete integrated IMA solution for up to 32 ports. All devices include a transmission convergence (TC) block to perform cell delineation, 512 K internal RAM to meet ATM forum requirements for differential delay compensation and a dual mode (UTOPIA or Serial) PHY layer interface. Source code for all required software functions is available from Mindspeed. The M28529 supports 32 IMA groups with 1-32 links per group while the M28525 supports 16 IMA groups and 1-16 links per group.

The TC block is capable of bit level cell delineation, which allows for direct connection DSL serial data streams without a frame sync pulse. Individual ports can be operated in a ‘pass thru ’ mode without the IMA overhead.

The devices provide designers with maximum design flexibility by including 3 PHY interfaces to choose from: UTOPIA Level 2, Serial TDM, or 8 MHz interleaved highway. In addition, an external memory bus allows the differential delay memory to access up to 2 Mbytes of external RAM. The M2852x supports both version 1.0 and 1.1 of IMA standard AF-PHY-0086.001.

Features

  • Complete IMA solution in a single package
  • 16 port, M28525
  • 32 port, M28529
  • Supports 50 ms (beyond the IMA standard requirements for 25 ms) differential delay with 512K Internal memory
  • UTOPIA Level 2 interfaces
  • Variable link data rates (64K?8.192 Mb/s)
  • Octet or Bit level cell delineation
  • Field tested software available
  • Up to 32 IMA groups with 1-32 links/group
  • Memory expandable to 2 M bytes via external bus
  • Glueless serial and interleaved highway interfaces to Mindspeed framers
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