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CX29704/2/1
OptiPHY™ - F155 Quad OC-3/STM-1 ATM/POS PHY
Overview
Description
The CX2970x family implements one, two or four-channel ATM and packet-over-SONET/SDH (POS) processing functions at 155.52 Mbps. The components contain both the PMD and TC sublayers and feature UTOPIA Level 2 interfaces to the ATM layer and POS-PHY Level 2 interfaces to the link layer. They also include dedicated serial ports for the insertion and extraction of the DCC overhead bytes.
Features
- Integrated CDR
- Clock recovery conforms to GR-253-CORE jitter requirements
- Low-power, 3.3 VCMOS technology
- Synthesizes a 155 MHz Tx clock from a 19 MHz input
- UTOPIALevel 2 and POS Level 2 system interfaces
Documentation
- Hardware Design Docs
- JTAG / BSDL Files
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CX2970x-13 BSDL Files (-13 Version) (11.01 KB)
July 11, 2002 -
CX2970x-14 BSDL Files (-14 Version) (10.79 KB)
February 13, 2003
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CX2970x-13 BSDL Files (-13 Version) (11.01 KB)
- Product Bulletins
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CX2970x Product Bulletin (60.91 KB)
August 27, 2002 -
CX29701/2/4 Product Bulletin (108.37 KB)
June 22, 2005
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CX2970x Product Bulletin (60.91 KB)
- IBIS Files
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CX29704-13 IBIS Files (-13 Version) (357.68 KB)
June 2, 2004
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CX29704-13 IBIS Files (-13 Version) (357.68 KB)
- EVM / Reference Design Guides
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CX29704 EVM User Manual (2.27 MB)
June 22, 2005
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CX29704 EVM User Manual (2.27 MB)
- Application Notes
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CX28250 Transitioning from CX28250 to M29701 Application Note (137.4 KB)
January 28, 2009
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CX28250 Transitioning from CX28250 to M29701 Application Note (137.4 KB)
- Sales / Marketing
- Product Briefs
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CX29704 Product Brief (360.91 KB)
May 8, 2001
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CX29704 Product Brief (360.91 KB)
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